Failure Analysis Workflow Example for Semiconductors

A device that fails only after thermal cycling, or only when a specific supply rail ramps, is not ready for decapsulation. It is ready for disciplined evidence collection. This failure analysis workflow example follows a practical semiconductor case: a packaged power device with elevated off-state leakage and intermittent breakdown during final test. The same logic applies to wafers, bare die, RF components, photonic devices, and board-mounted parts, although the instruments and physical access will change.

Why workflow order determines the quality of the result

Failure analysis is often described as a sequence of inspection and measurement steps. In practice, it is a process of preserving options. Every destructive action removes evidence. Every poorly controlled electrical measurement can alter a marginal device. Every comparison made against an unsuitable reference part can point the investigation in the wrong direction.

The objective is not simply to identify a visible defect. It is to establish a defensible connection between the reported failure, the electrical signature, the physical location, and the mechanism that caused it. For a failure analysis team, that means beginning with device history and repeatable behavior before moving into increasingly invasive techniques.

A useful workflow also prevents fragmented test setups. A probe station, source measure units, microscope, thermal hardware, light-tight enclosure, and suitable fixtures must work as one measurement environment. The best instrument in isolation cannot compensate for poor guarding, unstable contacts, inadequate current compliance, or an inability to control temperature.

Failure analysis workflow example: intermittent leakage in a power device

Assume an engineering team receives ten packaged MOSFETs from a qualification lot. Three show excessive drain-to-source leakage at room temperature. One of those parts also fails a breakdown test after a short period of bias stress. The initial question is not, “Where is the defect?” It is, “What exactly differs between failing and passing units?”

1. Define the failure signature and preserve device history

Start by recording the part number, lot, wafer or assembly identifiers, package type, test program revision, operating conditions, stress history, and pass/fail data. Include the failure threshold used by production or qualification. “High leakage” is not sufficient. A result such as 18 microamps at 60 V drain bias, gate and source grounded, after 125 C reverse bias for 30 minutes is actionable.

Retain untested controls from the same lot whenever possible. Also retain known-good units from a prior lot if the suspected mechanism may be process-related. The control population matters because nominal electrical limits may be too broad to reveal a meaningful shift.

At this stage, avoid repeated high-voltage sweeps on the failing part. If the device has a weak dielectric or localized junction defect, aggressive retesting can convert an intermittent signature into a permanent hard failure. Use current compliance and document every subsequent stimulus.

2. Reproduce the failure under controlled conditions

Repeat the original test condition first. Then perform a limited parametric characterization to determine whether the leakage is stable, voltage-dependent, temperature-dependent, polarity-dependent, or time-dependent. For the MOSFET example, this may include drain leakage versus drain voltage, gate leakage versus gate voltage, threshold voltage, on-resistance, and capacitance measurements.

A semiconductor device analyzer with guarded low-current capability is valuable here because the measurement may involve picoamp to microamp ranges alongside higher-voltage stress conditions. The test connection must be configured for the device architecture. Cabling, triax guarding, fixture leakage, chuck contamination, and probe insulation can all produce false leakage results.

Temperature is often the fastest discriminator. If leakage rises sharply with temperature and follows a consistent activation behavior, the mechanism may involve junction generation, contamination, or a field-enhanced defect. If the result appears only at a narrow temperature range or after a dwell period, mechanical stress, package interaction, charge trapping, or moisture-related effects may be more likely. The data does not prove a mechanism yet, but it directs the next measurement.

3. Inspect before opening the package

Perform external optical inspection before any internal access. Examine leads, mold compound, marking, package warpage, corrosion, handling damage, and evidence of electrical overstress. X-ray imaging can help identify wire sweep, bond-wire damage, die attach voids, foreign material, or gross package anomalies without disturbing the sample.

These methods have limits. A clean X-ray image does not clear the die, and a visible package imperfection does not establish root cause. Their value is that they identify obvious assembly issues and provide a baseline before decapsulation or cross-sectioning.

If the failure is associated with light sensitivity, include controlled dark testing at this point. A light-tight enclosure can distinguish genuine device leakage from photoresponse, especially in decapsulated parts, image sensors, photodiodes, wide-bandgap devices, and structures with exposed junctions.

4. Localize the electrical anomaly

Once the failure signature is repeatable, the next objective is localization. For a packaged device, this may require decapsulation that preserves bond wires and die surface condition. For a wafer-level issue, the die may already be accessible, allowing direct probing of pads, test structures, and suspect regions.

Mount the sample on a stable probe station with the appropriate thermal chuck, microscope configuration, probe arms, and safety provisions for the required voltage. Use low-force probing where pad damage is a concern. For sensitive die, a custom substrate mount may be necessary to provide repeatable orientation, backside access, or electrical isolation.

With the device biased near the leakage condition, use the available localization technique based on the expected mechanism. Emission microscopy may reveal hot-carrier emission from a localized defect. Liquid crystal or thermal methods may show heat generation. Optical beam induced resistance change testing can help identify resistive defects in applicable structures. Lock-in thermography can be effective when the defect produces a small, modulated thermal signal.

Technique selection depends on device type and access. A high-voltage defect may only become visible near breakdown, while a low-current leakage path may require long integration times and careful background control. RF and mmWave failures may need vector network analysis and calibrated on-wafer probing before a thermal or emission method will be meaningful. The workflow should follow the failure physics, not a fixed equipment checklist.

5. Correlate localization with electrical probing

A bright spot or thermal feature is a lead, not a conclusion. Confirm it electrically. On a decapsulated part, probe nearby metal, gate structures, source regions, or bond pads while monitoring the leakage signature. If layout data is available, compare the feature location to field plates, termination rings, via arrays, gate fingers, or known process-sensitive structures.

For the MOSFET case, the team may find that leakage rises only when a specific edge termination region is biased. Local probing could show that the behavior is concentrated near one source-side region rather than distributed across the active area. That distinction changes the investigation from a broad dielectric concern to a localized process, contamination, or handling issue.

Use a passing control under the same probe configuration. A comparison between failing and passing samples should use identical bias, temperature, probe placement, integration time, and instrument ranges. Without that discipline, small differences can be measurement artifacts rather than device behavior.

6. Use destructive analysis only to answer a defined question

After electrical and physical localization agree, destructive methods can test the leading hypothesis. Focused ion beam cross-sectioning, scanning electron microscopy, energy-dispersive X-ray spectroscopy, delayering, or material analysis may reveal a damaged dielectric, metal extrusion, contamination, void, crack, or process variation.

The key is specificity. Do not request a cross-section simply because the part has failed. Request it to examine a localized termination region, a suspected via, a bond interface, or a feature identified by prior evidence. This improves turnaround time, reduces sample consumption, and produces a result that can be connected to corrective action.

In this example, a cross-section through the localized edge region might reveal a dielectric discontinuity adjacent to a metal feature. The root-cause investigation can then expand upstream to wafer processing, passivation deposition, assembly stress, or electrical overstress exposure. A single physical defect may still have more than one possible origin.

Building a test environment that supports the workflow

The most effective failure analysis setups are configurable rather than oversized. A university lab evaluating bare die may prioritize a manual probe station, device analyzer, microscope, and temperature control. A high-volume reliability group may require automated wafer probing, software-driven stress sequences, guarded high-voltage connections, and data management across many samples.

Micron Probing helps teams configure these environments around the actual measurement path, including wafer-level, die-level, board-level, thermal, optical, RF, and cryogenic requirements. The practical question is whether each component supports the next decision in the investigation. For example, a thermal chuck is useful only if the system can maintain stable contact and collect comparable parametric data at each temperature point.

Budget also requires trade-offs. It may be more effective to build a precise manual probing and characterization station for early localization, then send a short list of well-defined samples to a specialized destructive-analysis lab. Conversely, teams with recurring failure modes may justify bringing optical inspection, dark testing, or automated stress capability in-house.

A good workflow leaves the team with more than a defect image. It leaves a repeatable measurement, a localized physical site, and a focused question for the next process owner to answer.